# What will computer chips look like in 2045?

Dwarkesh Patel · 2026-10-22

<https://dwarkeshpatel.podhood.com/0d59dadb-4eba-490c-a311-99ef4aad6767>

Dwarkesh Patel tours Intel's fabs to interview its technical leadership — process chief Chris Auth, CTO Pushkar Arundhate, and researcher Jack Cavalieros — about how future chips get built and why Intel could only double leading-edge wafer output with today's chipmaking tool stock while AI compute demand grows 3x a year. Auth explains 14A development across ~2,000 process steps, how Intel's 10nm delays came from over-innovating without EUV as TSMC adopted it four years earlier, and why backside power makes High-NA EUV worthwhile for Intel though not TSMC. Cavalieros covers ruthenium beating copper below ~20nm pitch and CFET stacked transistors. Arundhate argues fabs are ~80% fixed cost, the memory supply crunch exceeds compute's, fab costs double every 4-5 years, and only three advanced foundries remain.

## Questions this episode answers

### Why did Intel's 10-nanometer node get delayed, and what lessons did Intel learn from it?

Chris Auth explains 10nm had very aggressive targets, using 'hyperscaling' to scale faster than historically done without new tools because EUV wasn't ready. That burdened the process and engineers, delaying manufacturing. Intel now uses maturity metrics and phase gates, limiting innovation per node so schedules customers depend on are met.

[3:54](https://dwarkeshpatel.podhood.com/0d59dadb-4eba-490c-a311-99ef4aad6767?t=234000)

### Why is Intel exploring ruthenium interconnects when copper has higher conductivity?

Jack Cavalieros explains copper requires a liner, like a glue layer, to deposit and stick. Ruthenium can be etched directly, eliminating the liner. At very fine dimensions, roughly the 20-nanometer pitch range, trading off that resistive liner means ruthenium wins with better conductivity and resistivity than copper.

[30:02](https://dwarkeshpatel.podhood.com/0d59dadb-4eba-490c-a311-99ef4aad6767?t=1802000)

### Could the industry 10x leading-edge wafer production to meet AI demand?

Pushkar Arundhate says not 10x, but probably like 2x with today's global stock of tools, since EUV and other equipment face supply shortages and processes are locked into specific suppliers. Dwarkesh notes AI compute has grown 3x year over year for a decade, so that growth simply cannot continue without the entire supply chain ramping.

[50:43](https://dwarkeshpatel.podhood.com/0d59dadb-4eba-490c-a311-99ef4aad6767?t=3043000)

### For hybrid bonding, is die-to-die or die-to-wafer the better approach?

Tyler Osborne says Intel typically calls die-to-die wafer-to-wafer, bonding two full wafers, which dominates CMOS image sensors. But it requires dies that perfectly match, and randomization of good and bad dies means lost pairings. With chip-to-wafer, Intel can singulate and bond only known good dies to known good base positions, making it sensible for logic-to-logic.

[43:53](https://dwarkeshpatel.podhood.com/0d59dadb-4eba-490c-a311-99ef4aad6767?t=2633000)

## Key moments

- **[0:00] Intro**
  - [0:00] Intel leadership: AI demand is running 40–50% above maximum fab capacity — "never been as big a shock" to the semiconductor industry
- **[0:53] Building 14A**
  - [1:20] Intel's 14A node has been in development for 3+ years and requires fine-tuning about 2,000 individual factory process steps
  - [2:06] How chip yield actually improves month over month: inline metrology, end-of-line electrical test, and cross-sectioning defects in the TEM lab
- **[3:22] 10nm lessons**
  - [3:22] Intel's 10nm delay lesson: aggressive "hyperscaling" without ready EUV tools slipped the node from 2016 to 2018 and cost years
  - [4:52] Intel skipped EUV on 10nm because it wasn't ready — giving TSMC a 4-year head start that began volume production in 2019
- **[6:44] Transistor evolution**
  - [9:35] Q: Why did gate-all-around transistors take 30 years to reach production? Chris Auth on waiting until simpler wins were exhausted
  - [11:29] Chris Auth calls the post-2000 era the "golden age of innovation" — chip materials in use have grown roughly 10x since the 1990s
- **[13:13] Backside power**
  - [13:13] High-NA EUV explained: 0.55 numerical aperture prints features 1.7x smaller per pass on machines costing around $200 million
  - [14:27] Intel vs TSMC on High-NA EUV: backside power lets Intel print tight pitches in one pass, while TSMC must double-pattern with standard EUV
  - [16:39] Q: Why did Intel's 18A foundry PDK cause customer problems? Chris Auth on going from an IDM with no formal PDK to serving outside customers
- **[19:06] Future tech tree**
  - [19:06] Chris Auth's 2045 prediction: fully 3D chips with transistors, interconnect, and more transistors stacked into exotic structures
  - [21:49] The three limits of compute: switch speed, power per switch, and heat dissipation — and thermals are what block 3D logic stacking
- **[23:34] Hot Topics**
  - [24:27] Intel's Kevin Fisher: "You will never have a complete data set — if you wait for one, you've waited too long"
  - [28:41] Inside Intel's fab priority system: "Hot Box 1" wafers race through like a reserved carpool lane, at the cost of factory efficiency
- **[29:31] Research lab**
  - [29:47] Why Intel is exploring ruthenium interconnects: it beats copper below roughly 20-nanometer pitch by eliminating the resistive liner
  - [32:49] How CFET research works: short-loop test vehicles build one-transistor-on-one-transistor stacks years before full production readiness
  - [38:22] Where new chip materials die: failed adhesion, or a downstream process step that chemically destabilizes the film — a dead end
- **[40:00] Hybrid bonding**
  - [40:00] Hybrid bonding explained: fusing copper interconnects directly between chips, skipping solder bumps for far denser connections
  - [45:36] Packaging pitch has shrunk from 150 microns to 25 in volume production, with published reliability data already at 0.45 microns
- **[48:00] Supply crunch**
  - [48:13] Intel CTO Pushkar Arundhate: ASML makes fewer than 100 EUV tools a year and won't significantly exceed that even by 2030
  - [50:04] Intel CTO: today's global tool stock could only double leading-edge wafer output — while AI compute demand grows 3x a year
  - [51:30] A couple billion dollars of Intel CapEx yields chips that generate roughly $100 billion a year for AI model companies
  - [53:33] Why only three advanced foundries survive: ~80% of fab cost is fixed, so every point of utilization and yield compounds brutally
- **[55:16] Catching TSMC**
  - [1:00:13] Intel CTO's supply summary: production can beat forecasts next year, but 2030 output can't — tool lead times alone push orders into 2028
- **[1:01:02] Terrafab**
  - [1:03:01] Fab construction costs double every 4–5 years, and a High-NA EUV scanner with support gear already runs about $400 million
  - [1:05:18] Q: Do fabs even need clean rooms? Intel's CTO on questioning decades-old dogma in a risk-averse industry
  - [1:07:39] Intel CTO on tool stockpiling: "Had we known what we know today, we would have invested more like a year ago"

## Speakers

- **Dwarkesh Patel** (host)
- **Chris Auth** (guest)
- **Jack Cavalieros** (guest)
- **Pushkar Arundhate** (guest)

## Topics

Semiconductors and Chip Manufacturing

## Mentioned

ASML (company), Intel (company), Samsung (company), TSMC (company), 14A (product), 18A (product), Blackwell (product), CFET (product), EUV (product), High-NA EUV (product), backside power (product), finFET (product), gate-all-around (product), hybrid bonding (product), ruthenium (product)

## Transcript

### Intro

**Dwarkesh Patel** [0:00]
There's never been as big a shock to the semiconductor industry as the current surge in demand from AI.

**Pushkar Arundhate** [0:06]
AI is driving incredible computing demand.

**Jack Cavalieros** [0:10]
Easily 40% to 50% above our maximum capacity, which I've never seen before.

**Dwarkesh Patel** [0:14]
Progress in AI has been driven by exponentially increasing compute. To sustain that progress, foundries like Intel will need to manufacture far more leading-edge compute, both by producing more chips and by improving what each chip can do. But the production of these chips is bottlenecked by tools that Intel buys from their suppliers, most famously ASML's EUV machines.

If they don't have the equipment, they can't make the chips here.

**Dwarkesh Patel** [0:36]
I spent 2 days touring Intel's fabs to prepare for these interviews with its leadership. I wanted to understand what it takes to manufacture the world's most advanced chips, and how hardware is shaping the future of AI. Okay, I'm joined by Chris Auth, who leads development of all the processes that are currently under manufacturing.

### Building 14A

**Dwarkesh Patel** [0:53]
The thing I want to understand in more concrete detail is how the development of a new process actually happens. So if 14A is going to come out in 3 years, or 2 years from now, what is happening from now till then?

And I want you to walk me through as much detail as you can, everything from, like, the level of how is the yield improving, what kind of telemetry do you guys look at, what kind of experiments do you guys run.

I want to understand what is going to happen over the next 2 years as concretely as possible.

**Chris Auth** [1:20]
Yeah, and if we talk about 14A, 14A has actually been in development for about 3 plus years at this stage. And so quite a bit of pre-work has been done to get it to the stage that it's atright now.

Andright now we're getting very close to where we're finalizing the process, we're finalizing the tool sets that it will be manufactured on, and we're working on kind of the fine-tuning of each of the process steps. There's about 2,000 steps in the factory that you have to go do, and you need to do really intricate work at each one of those to make sure it's fine-tuned.

It can go into manufacturing, it can run thousands of wafers a week on this process, and it can be repeatable every single time.

**Dwarkesh Patel** [1:58]
Right now you might have a certain yield. Walk me through how that increases month over month. So there's a line running at 14A.

**Chris Auth** [2:05]
Yep.

**Dwarkesh Patel** [2:06]
What happens from now till next month that will result in the yield changing? How do you identify where the defects are? How do you fix that?

**Chris Auth** [2:12]
Yeah, so there's a constant process that we go through in identifying defects. And there's kind of two main ways that we'll identify defects. One is we have inline metrology. So we have tools that will look at the wafers and say, "Ah, there's a defect there, there's a defect there, there's a defect there."

And then also at end-of-line, either electrical test or we sort and see where the fails are, and we will identify failures, and then we will get analysis on those failures. We'll cross-section it. You were in the TEM lab yesterday, and you saw how you can get cross-sections.

You'll get a cross-section of a defect, and from that you'll be able to say, "Oh, that defect is between these layers, so it must have come from this section of the flow." Oh, we have inline metrology in that section, which has identified defects.

Those are the defects we need to go after. I think what we've learned is that you don't want to do too much innovation in one node, because the more innovation that you did, the more complex it becomes. And while that, yeah, you'll be able to get that to work, you need to hit a certain schedule, and that's the schedule that your customer ultimately wants.

So having that predictable schedule is a key piece. So you've got to figure out how much innovation you can put in in order to meet the customer's requirements in the timeline that they need it.

### 10nm lessons

**Dwarkesh Patel** [3:22]
Intel learned how costly that trade-off can be with delays to its 10-nanometer node, whose original target launch date was 2016, but which didn't begin manufacturing until 2018.

You know, usually Intel has been the keeper of Moore's Law, a new cadence of manufacturing every 2 years, but their last set of products slipped almost 4 years.

Intel today having its worst day in 4 months. The stock now down more than 15%. I also want to point out Taiwan Semiconductor up 13% off of Intel's bad news.

**Dwarkesh Patel** [3:54]
Walk me through what lessons you think Intel has learned from 10-nanometer.

**Chris Auth** [4:00]
10-nanometer was a good example of where we had very aggressive targets. We were doing what was called hyperscaling at the time, so we were scaling much faster than what had been historically done. And in order to do that, we came up with all sorts of innovative ideas and how we could achieve that without new tools, because the tools weren't ready.

And so that put a lot of burden on the process and a lot of burden on the engineers in order to do that. Now, at the end of the day, 10-nanometer is a great technology. It has world-class yield, it has world-class performance, it has world-class cost, but it took us longer to do that than what we would have liked.

And so we've kind of tried to take that learning into future technology nodes and say, "Hey, we need to limit the amount of innovation we put in there to make sure that we keep it on schedule."

**Dwarkesh Patel** [4:47]
What do you think was the main technology that should have been safe for a future version?

**Chris Auth** [4:52]
EUV was probably the big thing. When we started to define 10-nanometer, what the conclusion was, EUV was not ready.

**Dwarkesh Patel** [5:00]
EUV is extremeultraviolet lithography. It prints chip patterns with light at a wavelength of 13.5 nanometers, about 14 times shorter than that emitted by previous tools that chipmakers had relied on. The shorter the wavelength, the finer the features that a single exposure can print.

But Intel decided this technology wasn't going to be ready in time. TSMC transitioned to EUV much sooner. It put EUV into volume manufacturing in 2019 and ramped it up further on its 5-nanometer node in 2020. Intel's first EUV process did not reach products until 2023, so TSMC had about 4 more years of experience with these machines.

**Chris Auth** [5:42]
So yesterday we were at the research lab and we were getting a preview of 3D materials and CFET and ruthenium interconnects. And I'm curious about how you decide whether that technology is mature enough for the next node. One thing that did also come out of 10-nanometer is we started to define a set of maturity metrics.

And so we used those maturity metrics in a process, which we call phase gate, where we would say, "To go from pathfinding into development, these are the criteria that we need to go hit." And there's yield criteria, defect criteria, performance criteria.

And we need to hit those in order to move to the next set of the flow. And if there's something that doesn't make that, then it misses that and it goes on to the next technology, and we focus on the items that are ready and we can run and put into a process.

Because one of the key things is to stay on schedule.

**Dwarkesh Patel** [6:29]
Staying on schedule is hard partly because new transistor designs take decades to mature. Modern chip transistors evolved from the planar MOS transistor, demonstrated in 1960. The history of transistors since has been the progression from two dimensions into three.

### Transistor evolution

**Dwarkesh Patel** [6:44]
Each development that Chris goes on to describe, from finFET to gate-all-around, is a step in that progression. So it'll help to first look at a basic transistor and how its parts have changed over time. A transistor is basically a switch.

When it's turned on, it allows current to flow between its two ends, which are called the source and the drain. A piece called a gate sits on top of the silicon between the source and the drain. Applying a positive voltage to the gate turns the switch on, because the positive voltage pulls negatively charged electrons in the silicon beneath up towards the gate.

However, a thin layer of insulation stops them from actually reaching the gate, so the electrons collect just beneath that insulation and form a thin conducting path from the source to the drain. This is called the channel. Remove the voltage and the electrons disperse, the channel disappears, and the switch turns off.

As transistors shrank, the source and the drain got so close together that current could flow through the channel even when the switch was supposed to be off. We needed a better way to control the channel and prevent current from leaking through.

The fix was to give the gate a tighter grip on the channel by touching it from more sides. In the original planar transistor, the gate only touches the channel from the top. The finFET transistor squeezes the channel into a thin vertical fin of silicon.

The gate drapes over the fin so it controls the channel from three sides. The next progression from there was to cover not only the top and the sides of the channel, but also the bottom. This technology is called gate-all-around, and it slices the channel into thin ribbons, each of which gets completely wrapped around by the gate.

But getting gate-all-around to work required new materials and new manufacturing steps. To build these floating ribbons of silicon, you first sandwich them between alternating layers of a temporary placeholder material, which holds the space where the gate will eventually go.

We use a placeholder because the materials in the real gate wouldn't survive the processing that comes after, which involves baking the wafer at around 1,000 degrees Celsius. Once these hot steps are done, chipmakers etch away the placeholder, leaving the ribbon suspended.

Then they fill the gaps around every ribbon with a thin coat of a special insulator called a high-key material, whose purpose is to let the gate pull more strongly on the channel. And then on top of this material, they put the metal of the gate itself.

FinFET was demonstrated in a lab in 1989 and reached volume production at Intel in 2011. A gate-all-around transistor had been demonstrated a year earlier, in 1988, but Samsung didn't begin producing gate-all-around chips until 2022. So these ideas, finFET and gate-all-around, were developed around the same time, but they reached production a decade apart.

I wanted to ask Chris why it took so long to get to this current gate-all-around technology. Maybe you can walk me through then the process of getting into high-volume manufacturing.

**Chris Auth** [9:43]
Mm-hmm.

**Dwarkesh Patel** [9:43]
I want to understand concretely, once you have an idea that, "Hey, we're going to make the channel smaller, we're going to surround it," all the other problems of material science and figuring out how to not destroy the gate, how did they actually get figured out?

Why did it take so long?

**Chris Auth** [9:59]
Gate-all-around is a good example, because back in the '90s we knew of this idea. But we knew there was going to be these problems on how you put this into high-volume manufacturing. And at the same time, there's other things, like high-key metal gate, there's strain silicon, there's finFETs that are out there.

And so it's kind of like, when's theright time to go and tackle those? Well, you don't want to tackle something before you have to. And so if you have these other things that can drive performance, you would go and do that.

We went through this path where we did this. We did strain silicon, high-key metal gate, we did finFETs, and then it became, "Well, we need to do things further. How do we get there?" Well, gate-all-around is really the ultimate transistor out there.

Maybe it's time to go and start tackling some of those issues that you have. And you'reright, now you have to look at how do you put high-key metal gate in with gate-all-around. So it's that innovation that takes time.

Sometimes it's you need new materials, sometimes it's you need a different tool in order to be able to do some of the things that you need to go do. And that requires invention from the tool vendors. You have to go to the tool vendor and say, "Hey, I need a tool that can do XYZ.

I need a gas that can deposit this particular material that goes into that. I need a heating chuck that has this characteristic to it." All those things take time. And some of it's iterative, where you have to run a gate-all-around transition.

You say, "Oh, well, that didn't work. Let me figure out what was wrong with my hypothesis and try it again with some different structure."

**Dwarkesh Patel** [11:29]
How has the nature of R&D changed from the era of just making planar transistors smaller and smaller and just getting the benefits of denyard scaling to the world we're in today? Is it just a totally different kind of R&D process?

Where previously you were just like, "Let's make things smaller, smaller, smaller." Now you have to look at all these other facets of performance at the same time.

**Chris Auth** [11:49]
Yeah.

**Dwarkesh Patel** [11:49]
And the improvements in size don't come as easily. Walk me through whether there was some crucial change in the R&D process at that point.

**Chris Auth** [11:56]
If you look at the '80s and '90s, yes, it was driven really by denyard scaling, lithography. We just make things smaller, transistors got faster, they got more reliable, and it was very predictable cadence. When we started to hit 2000s, what we saw was, "That's not good enough anymore.

We need to do something different." And to me, it became this golden age of innovation. For each technology node, how are you going to provide more scaling? How are you going to provide more performance? And so it drove things like strain silicon.

It drove high-key metal gates. It drove finFETs. It drove gate-all-around. It drove backside power. These are things that were in the '80s and '90s. You would be like, "Oh, no, we're not touching any of that," because we just continued to have the same process flow.

We just scale it, scale it, scale it. But that's really, for somebody like me who's a transistor junkie, it's awesome, because now the playbook's open. You can do all sorts of things out there. You can bring in new materials.

I mean, just look at the number of materials we used to use in the '90s versus the materials today. It's probably gone up 10x. And there's a lot of innovation. There's atomic layer depositions. I mean, just you're controlling atom by atom this stuff.

So it's changed a lot how you approach the process as to before it was try to not change anything, to now it's like, "Take the sledgehammer and start just tearing the thing up and come up with some new idea."

### Backside power

**Dwarkesh Patel** [13:13]
For 14A, Intel is using a new kind of lithography machine, High-NA EUV. It uses the same extremeultraviolet light as today's EUV machines, but changes the optics. NA, or numerical aperture, is a measure of how wide a cone of light the machine's mirrors can focus onto the wafer.

The wider the cone you can focus, the smaller the spot that your light can carve. Standard EUV machines have an NA of 0.33. High-NA widens it to 0.55, so High-NA can print features about 1.7 times smaller in a single pass.

When features are smaller than the lithography machine can print, chipmakers have to split the pattern across several passes, each printing a different set of features. The most tightly packed patterns can require two, three, or even four passes. Each additional pass takes up valuable time on a machine that costs around $200 million, and it introduces another opportunity for defects.

High-NA machines cost about twice as much, but they can reduce the number of passes that are needed. So the question which determines whether they justify their higher price is how much more time they save and how much they reduce the risk of defects.

Now you guys are using High-NA EUV tools for 14A, whereas TSMC has said that they don't make economical sense yet for them. How do you decide whether the next litho tool is the one that is ready to adopt or not?

**Chris Auth** [14:42]
Yeah, and High-NA is a good example of where, because of the architecture of our technology versus TSMC's, we make different conclusions off of the same tool set. We use backside power. That means that you actually alleviate some of the pitch requirements you have on the front side.

And that allows you to print that directly with High-NA. TSMC has to run very tighter pitches because they don't have backside power, and they can't do that with High-NA, so they have to use double patterning EUV. So for them, it's not very helpful.

For us, it is very helpful. Now at 14, we've left it as an option, and it's something that we'll have a discussion with the customer on, because there's some value proposition of it. There's some complexity that it adds.

**Dwarkesh Patel** [15:26]
Chris is referring to a feature called backside power. A chip has two different kinds of wiring. Power lines deliver electricity to the transistors, and they need to be thick. Signal lines let the transistors talk to each other. They're much thinner, but they need to be spaced apart so that the signal from one wire doesn't interfere with the signal from another.

In the past, all of these power lines and signal lines had to be crammed together on top of the transistors. Intel's newest process moves these power lines below the transistors to the back of the wafer. This frees up space on top, so the signal lines don't have to be packed as tightly.

This change makes High-NA worth it for Intel. Without backside power, the wiring is so tight that it would require multiple passes to print, even with High-NA. With backside power, a single High-NA pass is enough. Outside companies can now commission Intel to manufacture chips that they've designed.

They follow Intel's Process Design Kit, or PDK, the menu of what a given process can build and the rules for building it. Do you need to lock that into your PDKright now for customers who are planning on developing on 14A?

**Chris Auth** [16:31]
It's an option in the PDK today, and we're handling it as a customer-by-customer discussion that we have as to whether or not they want to go down that path or not.

**Dwarkesh Patel** [16:39]
So for 18A, there's public reporting that there were delays or issues with the PDK such that some instructions didn't work, and it was difficult for people to use your foundry to build their chips. Tell me about the process of Intel becoming a foundry and then having a PDK that other customers can use to make whatever chip that they're making as well.

**Chris Auth** [16:59]
There's definitely a learning curve to how you become a foundry, and that's something that our competitors have gone through as well. PDK is a good example of that. For decades, we've been an IDM, and we've gone to our product teams, and we've shown them our transistor data, and we share that data back and forth, and we haven't had a formal PDK-type process.

So that's a new process that we've had to go implement on 18A. And 18A started out not having a PDK. And so there's definitely a lot of feedback we've got from the customers as to what they expect for quality and maturity of the PDK, what sort of information that they want to see in there.

And so we've tried to incorporate that into making sure that, "Hey, we have a PDK that meets our customers' requirements." And I think that's where we've ended up, is that we're starting to get PDKs that have this. And 14A will have that from the get-go.

It has very high-quality PDKs. Again, there's maturity metrics for what is a PDK .5 versus a .9 versus a 1.0. And we're constantly going through and taking customer feedback and incorporating that into the quality of our PDK.

**Dwarkesh Patel** [18:01]
For most of its history, Intel's fabs made only Intel's chips. That could be part of what allowed TSMC to gain an edge. Serving many customers gave TSMC more wafers to learn from, more revenue to reinvest, and more pressure to hit deadlines.

Basically, all enterprise customers have a shared set of product requirements that you have to meet if you want to even start talking about doing business with them. These are things like SSO, so employees can log into your app with their company accounts, or directory sync, so that whenever someone leaves, their access gets shut off automatically.

These features are harder to getright than you think, and the risk-reward for building them in-house doesn't really make sense. A slightly better version of SSO probably won't accelerate your growth, but a broken one will definitely stunt it. WorkOS gives you access to battle-tested versions of all the most common enterprise features, things like SSO, SCIM, RBAC, audit logs, and more.

WorkOS also has versions of these features that are purpose-built for agents, so they can log in, grab theright permissions, and take actions within your product. All of these features can be plugged in with just a few lines of code, so you can add them and get started selling to enterprises.

### Future tech tree

**Dwarkesh Patel** [19:06]
OpenAI, Anthropic, and Thinking Machines, as well as more than 3,000 other companies, all rely on WorkOS to meet their enterprise requirements. If you want to join them, go to workos.com and tell them that I sent you. If a butterfly flapped its wings in the '60s, could you imagine a world where gate-all-around is not even a word people have heard of or an idea people are familiar with, but people are thinking of an extremely different branch of the tech tree?

And how far down the tech tree do you think things could be totally different? Could it be like we're not even using copper?

**Chris Auth** [19:35]
If you look at, say, transistors and interconnects, I think where we've gotten to, as far as the transistor and gate-all-around and it being the ideal transistor structure that I have, I think with someone in, as I said, in the '90s, we were already talking about these type of things.

Backside power, that one's pretty out there. I think even in the '90s, the idea that you're going to strip off the entire silicon substrate and put lines on the backside side, that one is probably something that's a little bit out there.

Copper, of course, copper wires are the best, so I don't know how you would end up somewhere else besides copper.

**Dwarkesh Patel** [20:13]
But you guys are exploring other—

**Chris Auth** [20:15]
I think for some of the very tightest pitches, I think it's enabled that you will replace copper. And so that's a good example of where you will have another material that will come in there. But for the larger lines, I think copper is about where it's at.

I think that once you start to do gate-all-around transistors and you do backside power, now you start to enter a very different regime, because now you see it's not, "Hey, there's just some substrate, and you stack everything on top."

Now you've got a transistor, which is floating in interconnect. And you're like, "OK, well, why don't I have transistors, interconnect, and more transistors, more interconnect?" This whole 3D stacking that we now do with just discrete chips that we stack on top of each other, now you're like, "Why can't I just build an entire structure like this?"

You see it with memory, NAND, DRAM. They have some incredible 3D structures. NAND already does it. DRAM talks about it, but I think that DRAM inevitably is going to go there, too. So a lot of people say, "Oh, no, we're not going to do this because, hey, we can't do it in the next five years."

Well, come on. Let's put a larger timescale on this. Let's put 10 years, 20 years. In 2045, do you think you could do it? And now you start to say, "Oh, yeah, I could see us having some pretty exotic structures at that point."

So we limit ourselves by what we see as possible in the next four years, because as I've always said, when people say, "Hey, how do you see technology scaling going?" Yeah, we have visibility about four years. And then you get out to that four years, and you go, "Yeah, I think there's something we can do another four years out of that."

And then you get to that four years, and you're like, "Yeah, I think you can do something." But if you start to talk about 10 years, yeah, it becomes hard to say what it's going to be.

**Dwarkesh Patel** [21:49]
Chris's idea of building upwards could start with the transistors themselves. Chips use two types of transistors called N-type and P-type, which work the same way, but with the charges reversed. Nearly every circuit is built by pairing them up.

Today, chipmakers build them side by side. The next step is to stack them directly on top of each other in order to save space. In principle, that fits twice as many transistors into the same area. This design is called a CFET, short for Complementary Field Effect Transistor.

But every extra layer adds manufacturing steps and cost, and also leads to heat building up that doesn't have a clear way to escape. Because logic consumes more power than memory, you can't do stacks of DRAM that make HBM or 3D NAND as easily with logic because of the heat issue.

Is that the fundamental issue then over the long run? Is how you build the CPU?

**Chris Auth** [22:44]
Yeah. So there's three things that you have when you try to say, "Hey, what limits compute?" It's how fast can you do the switch, so the frequency of the device. How much power does it take in order to do that switch, so the power efficiency of it?

And the second one is how do you dissipate the heat that was generated by doing that switch? And that's the thermals piece of it. And I think the thermals piece is, and these are not new problems. You can go back 20 years, and you can see articles on these three things.

And so the question is, yeah, thermals, how do you deal with that, particularly when you start to talk about these 3D-type devices? I think that there is a need for that sort of system-level analysis and simulation tools. I think we're at its infancy because we've just started to look at this.

But it is a limiter, and it will be a limiter. But again, these are problems that we can go solve.

**Dwarkesh Patel** [23:34]
The problems respond to work, but engineering time is finite, and so are the wafers for experiments. Deciding where they go across thousands of problems is itself one of the hardest parts of bringing up a node. I sat in on one of Intel's Hot Topics meetings where those decisions get made.

### Hot Topics

**Dwarkesh Patel** [23:50]
OK, I'm here with Kevin Fisher, who was laying down the law this morning at the Hot Topics meeting where you guys were discussing how you're improving 18A and 18AP technologies. And people would come to you with these different experiments they were running, different ideas they had for improving yield and improving performance.

And then you and your integration engineers would tell them what data you needed, tell them how they should proceed, tell them how you think you can move things faster. And people would have a sense of the culture of these meetings.

So one thing that I found striking is just that there's this bottlenecking, your most advanced node, you want to progress happen fast. And so you kind of lay down the hammer.

**Pushkar Arundhate** [24:27]
I would say the average engineer doesn't understand

the stakes or theurgency of how this is going to impact Intel's bottom line, how it's going to impact our customer. They just have no visibility to those issues. So they will typically have

a certain set of criteria that they want to go capture. They'll hit boundaries of, "I asked for something, and someone said no, and I'm done. I guess I can't have this thing that I asked for." One thing you learn in this industry is that you will never have a complete data set.

If you want to wait for a complete data set, you've waited too long. It's already too late. So a lot of what I end up doing in those meetings is I decide how much risk we're going to take on a certain decision or not take on a certain decision.

And you need to say, "Look, do we go now? Do we start risking production?" Because you're risking the bottom line. You're risking revenue. I'm worried you're going to put me in the light of being an ogre because I'm putting the hammer down on people.

**Dwarkesh Patel** [25:38]
That's a great reputation to have.

**Pushkar Arundhate** [25:39]
It's really conveyingurgency. Every day counts.

**Dwarkesh Patel** [25:43]
Yeah. Can you walk me through a particular issue that might come up?

**Pushkar Arundhate** [25:47]
Well, one of the examples you saw this morning, which is EPI nodules.

**Dwarkesh Patel** [25:52]
EPI is short for epitaxy, which means growing new material on top of an existing one. Chipmakers flow gases over a heated wafer, and the gases leave atoms on its surface. The crystal structure of the material underneath acts as a template.

Each new atom lines up with the atoms below it, and the new layer continues the same crystal. Chipmakers use epitaxy at several stages of making a chip. In the step Kevin describes, they use it to grow the source and the drain as small crystals on either side of the gate.

**Pushkar Arundhate** [26:21]
So during the deposition of our epitaxy, we get abnormal growth, like a tumor. It's going super fast. And that causes problems because one EPI will short to the wrong EPI, and you get transistors not working. And then you've got to narrow it down to how are you going to fix it.

**Dwarkesh Patel** [26:39]
For the past decade, Intel's chips have had this feature called Processor Trace. When you turn it on, it starts recording all the code your program runs, and it captures enough detail that it can go back later and reconstruct every single function call.

Most companies don't need that level of detail, but Jane Street does. They need to investigate specific fleeting moments in their trading systems, things like a delayed response to a network packet. Those events tend to be too brief for most debugging tools to catch.

So when one of Jane Street's engineers noticed Processor Trace, he started playing around with it. And then he and a summer intern turned that exploration into a new tool called Magic Trace. Magic Trace leverages the output from Processor Trace to give Jane Street a history of every function call leading up to a specific moment of interest.

This project was completely bottoms-up. It started just as something that one engineer thought would be valuable. And now traders and developers across Jane Street use Magic Trace every single day. If you want to work somewhere where you're trusted to pursue the ideas that you think matter most, Jane Street is hiring researchers and engineers.

Go to janestreet.com/dwarkesh to learn more.

**Pushkar Arundhate** [27:46]
One of the pieces that you observed this morning was a special clean that we were looking at, which would eliminate the nodule. So the nodule would deposit, and then we'd get rid of it. Some of the other discussion was, well, the source of the nodule, get rid of the source of the nodule.

**Dwarkesh Patel** [28:01]
So how do you decide what there's some issue, how do you decide what the source of it is?

**Pushkar Arundhate** [28:06]
For the most part, we work highly parallel. So how do you decide? It's not always evident what the easiest way to fix the problem is. So you work on all the potential fixes. And sometimes it's not the one you expect first.

Once we've identified it as a primary problem for the technology, that's where this Hot Topics meeting gets involved. And that's how we align the resources into those engineering teams so that we can accelerate the work.

**Dwarkesh Patel** [28:35]
You said that there's some fast-track process where wafers can move through faster if they're bottlenecking some experiment.

**Pushkar Arundhate** [28:41]
So we have a tiered system of what we call hot boxes in the factory. And every grade of hot box goes a little bit faster. And it's just how the factory prioritizes that particular lot, that block of silicon that's running through the factory.

So our highest grade of hot box, Hot Box 1, races through the factory. It gets priority at every single tool. But it's a drag on the entire factory. If you had a factory person in here, they don't like using playing that card because you're ending up using the tools inefficiently so that you can go super, super fast.

Think of it as a highway, and you set aside that one lane for the carpool, which everyone could use, but you're saying, "OK, it's just the carpool." That's our Hot Box 1. Everyone clear out of that lane except for that one experiment.

And that one experiment races down the highway.

**Dwarkesh Patel** [29:31]
Kevin's job is deciding what goes on the production line now. But the day before, I went to Intel's research lab with Jack Cavalieros to see ideas that aren't ready for the node yet. We started with wiring. A transistor is only useful once it's connected to others.

### Research lab

**Dwarkesh Patel** [29:47]
And on a modern chip, that takes more than a dozen layers of metal wires stacked above the transistors called interconnect. These wires are made of copper. And as they shrink, copper starts to run into trouble. Intel is exploring a replacement, ruthenium.

Ruthenium has higher resistivity. So why are you guys exploring ruthenium for the future?

**Jack Cavalieros** [30:05]
So interestingly enough, as you scale the dimensions of those copper wires, you run into challenges. For example, copper requires typically a liner in order to deposit the copper to fill those lines. Ruthenium is very different in that regard because it's a material that we can actually etch.

And as such, by etching it, we don't need that liner. So now you scale those very fine dimensions. And if you can trade off that resistive liner with no liner, ruthenium starts to win. So there is a crossover point that ruthenium will have much better conductivity, better resistivity than copper.

And that's roughly in the 20-nanometer pitch range, which means if you can imagine half of the pitch is your metal line and the other half is the dielectric that isolates.

**Dwarkesh Patel** [30:55]
So what is the liner?

**Jack Cavalieros** [30:56]
The liner is think of it almost like a glue layer, a transition layer that we need in order to deposit the copper and have it stick and make that connection to the copper lines below it. These are all interlocking copper lines that interconnect to each other.

But every time you deposit copper, you've always had a liner underneath it. And in the past, that liner may have been a significant portion of the entirety of that conduction path. But over time, we've scaled it, made it thinner.

And so copper comes back into play as a contender.

**Dwarkesh Patel** [31:28]
One thing I'd be curious to know is how you decide that a technology is mature and ready for high-volume manufacturing. So with 10nm, you're mentioning you guys moved on from copper to cobalt, and there were potentially issues with that.

How do you decide that this technology is going to work at scale?

**Jack Cavalieros** [31:46]
So the integration of these materials into such a complex system as the transistor ecosystem involves many, many different components. The scalability is one part, but its ability to integrate is another. At the time we made a decision for cobalt, it was the forerunner.

The results were stronger at the time. But as we work with our ecosystem externally, the vendor ecosystem that provides these materials and the tools that we integrate them with, we find solutions down the road that may bring copper back in line as being the stronger of the two.

And that's exactly what happens. Every technology that we go through, we will evaluate multiple options. And as we get closer to our time horizon for delivering a manufacturing-worthy product, we have to make a decision. And the leading option at the time was cobalt.

Now it's copper again. And perhaps in the future, it'll be ruthenium.

**Dwarkesh Patel** [32:42]
I'd love to get your thoughts on CFET, basically stacking the transistors on top of each other.

**Jack Cavalieros** [32:49]
Yeah.

**Dwarkesh Patel** [32:49]
What is progress like there? Can you keep making more and more layers? Is it just two? Can we go three, four? How high can you get?

**Jack Cavalieros** [32:55]
Yeah, so that evaluation of CFET is currently underway, not just by us, by our competition. Labs externally are looking at it. It is the ultimate in stackability. We're taking transistors that had to be compressed more and more, and we're relaxing that in some ways because we're going to stack them on top of each other.

But the act of stacking does not mean that they're not interconnected. What used to be connections on the top or even on the bottom, as you've seen from our press release, now has to go vertically in between the transistors.

And that's a new challenge because the aspect ratio of creating trenches and filling those trenches becomes more and more difficult. So it's not as straightforward as stacking the transistors because you still have to think about interconnecting them.

**Dwarkesh Patel** [33:41]
Is the issue there the etch to get that deep hole?

**Jack Cavalieros** [33:43]
Aspect ratio for the etches is a big part of it. We're working with our vendors to evolve on that. But it's also what you fill those very tiny spaces with because filling can sometimes leave air gaps or holes that never really fill.

And that's not ideal.

**Dwarkesh Patel** [33:59]
I assume there's a version of CFET that works inside this lab.

**Jack Cavalieros** [34:02]
Yeah.

**Dwarkesh Patel** [34:02]
What is the kind of wafer or process or whatever that is workingright now? Then what's the next step? What's the next step? What's the next step until it's inside the full high-volume process?

**Jack Cavalieros** [34:13]
Part of the process of evolving these technologies, especially something more complex like an architecture, not just a basic chemistry or a material, but a full architecture like CFET, is that we have to make short-loop vehicles that can give us faster turnaround.

The normal manufacturing process can take a month or longer to complete the thousands of steps that it goes through. Our goal here is to take unit cells of that process and qualify them. So we take advantage of short-loop vehicles that can give us electrical parameters, chemical parameters that can resolve some of those challenges, those speed bumps.

And once we've resolved them, then we combine them into a more complex test vehicle. So what you would find in here is something very simple. You might be making a diode. You might be making a capacitor, which are components of the transistor.

And as those evolve and become stronger, better performing, you combine them to make the next stage, which might be the transistor itself. So in the CFET example, you might not choose to do four ribbons on top of four ribbons.

You might just choose to do one on one because naturally, the aspect ratio of dealing with something that much taller becomes more and more challenging. So we would have a simplified version of a CFET, which has only one wire for the NMOS and one wire for the PMOS.

And that simplifies our job, but it still helps us evaluate the stacking of devices and how they will interconnect.

**Dwarkesh Patel** [35:48]
But are the feature sizes here as small as they will be eventually, or are the feature sizes bigger?

**Jack Cavalieros** [35:52]
Oh, absolutely. In some cases, at least as small. For example, you've heard of 2D materials, these transition layer dichocolagenides, as they're called. They're very, very thin materials. They're essentially one monolayer of atoms that we deal with. Those depositions can happen in this lab.

We can evaluate those films in terms of conductivity, our ability to contact them, our ability to modulate that conductivity, which is what the transistor does. So yes, we do have the ability to not only deposit films that are very small and thin to the atomic scale, but also print very small features.

We have EUV technology that can or e-beam technology that can allow us to print very small features similar to what we will eventually make in production.

**Dwarkesh Patel** [36:43]
So I guess I don't understand

intuitively, lacking the context in this process, why that you have the features that are as small for a working CFETright now.

**Jack Cavalieros** [36:57]
Yes.

**Dwarkesh Patel** [36:58]
Why will it take 10 years for it to be in my phone? I understand it is like a process, but why is it such a long process?

**Jack Cavalieros** [37:06]
The answer is slightly different when you're dealing with an architecture like CFET versus a novel material. Materials have, of course, the challenges of being deposited, etched, removed, their compatibility with other layers above and below. All those things have to be researched first before you put them in a production line.

An architecture may seem like a simple evolution. Oh, you're making nanoribbon transistors next to each other. What's wrong with just stacking them? But the act of stacking them, of course, increases the aspect ratio for etches, depositions, cleans, and the technology may simply not be ready yet.

**Dwarkesh Patel** [37:44]
But if you've already made it here, there's a version of the technology that's ready,right?

**Jack Cavalieros** [37:50]
Correct. So we've made a simplified version that may not be an advantage over our current planar side-by-side technology of nanoribbons. But we need to evolve it to make it maybe two nanoribbons or to add theright type of metals and dielectrics in order to extract the maximum performance out of that device.

**Dwarkesh Patel** [38:10]
Got it. OK, so it's like a long tail of.

**Jack Cavalieros** [38:13]
There's a thousand different steps that all have to come together in a very unique way to make the performance compatible or actually supersede the prior technology.

**Dwarkesh Patel** [38:22]
Where do the ideas tend to fail? So you have like 20 ideas that are like 2D materials.

**Jack Cavalieros** [38:27]
Correct.

**Dwarkesh Patel** [38:28]
What is the kind of way in which you're like, this is actually not worth pursuing further?

**Jack Cavalieros** [38:32]
Sometimes the idea becomes something that we discover fundamentals about the material that will be incompatible with the rest of the processing that we do. At first, the first level of experiments may simply be very simple depositions. And you say, OK, I can deposit the film.

I can look at it. I can measure it. But the moment I try to make a contact to it, nothing sticks. It could be something fundamental as simple as the adhesion of the next step in the process simply has no way to adhere to the material.

So you may rule out a material because of something as simple as that. More complex challenges might be the subsequent processing may have gaseous interactions with downstream steps. So for example, I've deposited the film. I've capped it with other materials, but they're not hermetic.

And so my third or fourth or fifth step in the process may actually still interact with it and change its properties. That makes it unstable. And now we have to find better hermetic sealing for that process. And if we don't find a way to control it, then it's a dead end for us.

**Dwarkesh Patel** [39:46]
Stacking transistors is still in the research lab. Stacking whole chips is already in production, and it tackles a different problem: how separate chips communicate with each other. Modern computers are divided into multiple parts, each optimized for a different task.

For example, NVIDIA's Blackwell data center GPU joins two huge processor chips and surrounds them with eight stacks of high-bandwidth memory. These chips have to constantly send data back and forth with each other. And in AI, the speed of that traffic, not the raw computation itself, is often what limits how fast the workload finishes.

### Hybrid bonding

**Dwarkesh Patel** [40:20]
Imagine two chips side by side, communicating through their facing edges. If you double each chip's width and length, you'd have four times the area for circuitry, but only twice the edge length for connections. This is the area versus perimeter problem.

As transistors become denser, a chip's ability to do computations increases faster than its ability to move data around. The industry has known about this problem for years, so multiple technologies have been invented to address it.

The completed circuits must undergo two last operations: bonding and packaging.

**Dwarkesh Patel** [40:52]
Once a chip is made, it still has to be connected to other chips and to the rest of the computer. That step is called packaging, and it has changed a lot in the last few decades. At a high level, you can think of the evolution of packaging like this.

Initially, chips were laid out side by side. Wires connecting them went out the side of one chip to another. To allow for more communication density, the industry introduced a shared piece of silicon called an interposer for multiple chips to sit on.

A chip can talk to other chips through the wiring that runs directly through the interposer. This type of packaging is often called 2.5D. Another way to increase connection density is to bond chips directly to one another. This allows for shorter connections between chips.

But the early versions of this idea used solder bumps, which are bulky and increase resistance. It would be better to skip the solder and fuse the signal wire connections of the two chips directly to each other. This is called hybrid bonding, and it is one of the technologies the semiconductor industry is investing in the most.

Hybrid bonding works by aligning the copper interconnects of one chip with those of another. Then these chips are pushed together and heated so their interconnects expand and bridge the gap between the chips. This process makes the insulating surfaces around the copper bond as well.

And so by removing the solder bumps, you end up with much denser connections. But the reason this technology is only now entering volume manufacturing is because it took a while to iron out the alignment and defect challenges that it introduced.

In the packaging lab, I asked Tyler Osborne, a director in Intel's Advanced Packaging Technology Development Group, how they put this into practice. Intel has spent over 50 years optimizing its CPUs for speed. But lots of these optimizations, like caching and branch prediction and speculative execution, reduce predictability.

The exact same instructions can take four cycles to execute one time and 300 the next. When you stack billions of instructions together and execute them across multiple threads and cores, these non-determinisms compound into all sorts of hard-to-reproduce bugs.

If you work on serious systems, you've definitely experienced this. Antithesis solved this by doing something a bit crazy. They built a 100% deterministic computer. They identified every single door in Intel's x86 architecture where non-determinism could leak in: network packets, disk reads, temperature sensors, even time itself.

And they either welded each of these shut or slotted in a controlled simulation. This deterministic computer is just the foundation. On top of it, Antithesis built a testing platform that compresses years of production hardening into minutes and runs your software through thousands of parallel worlds, injecting faults and intelligently steering each one towards a one-in-a-billion failure that you'd never be able to test yourself.

This determinism is what's behind all the other insane Antithesis features that I've mentioned over the past few episodes. It's what lets you reproduce any bug and time travel to any point in the test run. Most importantly, it's what lets you or your agents trace every failure back to its root cause.

Go to antithesis.com/Dwarkesh to learn more.

Two different ways you could do hybrid bonding is die-to-die and then die-to-wafer. And maybe you can talk about the advantages of both and which one actually practically works better.

**Pushkar Arundhate** [44:03]
Sure. So actually, around Intel, typically, I think as you're referring to die-to-die, we typically call it wafer-to-wafer. So we actually take a full wafer and another wafer and bond them together. That's an approach that's really popularright now in the CMOS image sensor industry.

In fact, it basically dominates it. And it's being looked at for other things like memory stacking, all kinds of stuff people have published ideas about. One of the challenges with that, though, is that you need dies that perfectly match each other and are perfectly like left-handed andright-handed,right?

So you have to be able to pond exactly one to the other. So one-to-one die size is a challenge. So if they're not the exact same designed device on top and bottom, that's a problem. So wafer-to-wafer, it's just challenging to make sure that you have wafers that match really well in terms of the sort,right?

So sort good array here versus sort good array here. If they match exactly, good die and bad die, that they all match, I can get 100% yield of that operation of the good dies. But the chances of that are very low.

It's going to be some randomization of the two. And whatever that randomization is, it's just going to be loss of good bonding to bad. Whereas at chip-to-wafer, I can dictate the terms,right? I can singulate and have known good dies that I've tested at the chip level and then only bond known good to a known good base position.

**Dwarkesh Patel** [45:17]
Do you think then chip-to-wafer is the way that you'll do hybrid bonding in the future?

**Pushkar Arundhate** [45:20]
I think we're going to do both. We definitely have the capability to do both. It's really customer and architecture-driven. But certainly, chip-to-wafer in the logic-to-logic space makes a lot of sense.

**Dwarkesh Patel** [45:29]
So you were explaining that going from advanced packaging to hybrid bonding, the size of the pitches is decreasing. How much further could that go?

**Pushkar Arundhate** [45:36]
That's a wonderful question. So historically, like we were saying, 15 years ago, first level interconnect was 130, 150 micrometer pitch. Today in HVM, we're doing 25 micrometer pitch in Volvo ROS. Here, we're doing sub-10. But there's already been literature out there.

In fact, the biggest conference every year in packaging is the IEEE ECTC conference that happens in May. And there was a paper there this year showing reliability data on a 0.45 micron pitch hybrid bonded device. So you can imagine that's a whole nother order of magnitude in density again from where we areright now on HVI and scalability that's already been proven.

So I see a long runway there.

**Dwarkesh Patel** [46:19]
Within interconnect, within a single wafer, how far separated are they usually?

**Pushkar Arundhate** [46:23]
So the back end of the fab, you can imagine like the few layers below packaging are typically around one micron to a half micron in size. So if you can push packaging down to 0.5 microns or below, we can start you can almost think about taking layers off the top of the die and connecting to a lower layer within the silicon to another lower layer within the silicon,right?

That's really kind of where the beauty of hybrid bonding happens. You could think someday about even having reduced interconnect layers on both sides that we can bond together and have less total IR drop between the two transistor layers.

It's really kind of cool to think about where that could go once we get into those regimes.

**Dwarkesh Patel** [47:04]
Actually, I am very curious about for AI, it makes sense why hybrid bonding is so powerful because then you can get like higher bandwidth of the memory.

**Pushkar Arundhate** [47:11]
Absolutely.

**Dwarkesh Patel** [47:12]
But you're saying with issues with heat and everything, what is the advantage for non-AI applications of hybrid bonding?

**Pushkar Arundhate** [47:18]
Excellent question. So there are companies out there that are looking at it for non-AI applications, even in fact, in client devices,right? And one of the big things I think that that can help with there is, well, number one, obviously, the same raw interconnect density, especially between something like a CPU and a GPU.

But the other one is around power,right? So like we talked about before, as you get to finer and finer interconnects, you can reduce the total power consumption in pico joules per bit for that interface. So with hybrid bonding and those applications, you could think about that as another way that packaging can help reduce the total system power budget.

**Dwarkesh Patel** [47:53]
Interesting.

**Pushkar Arundhate** [47:53]
So then that gives you lots of benefits,right? Lower power, less heat for the same benefit in terms of actual electrical performance.

### Supply crunch

**Dwarkesh Patel** [48:00]
So far, this has been about making better chips. The other half of the question is how many chips the industry can make if AI labs are willing to pay for far more of them. I'm going to get a chance to talk to Pushkar Arundhate, who is the CTO of Intel.

I'm very interested in understanding how the fact that the entire industry has to rely on the same suppliers brought an extra ability to ramp up production. So for this EUV tool, ASML produces less than 100 of them a year.

**Pushkar Arundhate** [48:26]
Yes.

**Dwarkesh Patel** [48:26]
And they don't plan to produce more than 100 a year, even by the end of the decade, or significantly more than 100 a year. And that has to be split between you, between TSMC, between all the memory makers who are ramping up production like SK Hynix.

How does that limit your ability to scale up to all this demand?

**Chris Auth** [48:40]
It is a limiter. So we have to make the most of the capacity that we already have installed. And we'll try to increase the output from our existing fleet of tools. And EUV or ASML is not the only bottleneck.

It is definitely a bigger bottleneck than some of the other tools. But to a large extent, we're seeing all equipment seeing tremendous supply shortage. Even though there are multiple providers of other tools, once you lock into a process flow, let's say 18A,right?

18A is a mature process now. So we need a specific tool. We can't just go and get a different tool for the same. So therefore, we're locked into that one tool, one supplier. And so we rely on that.

**Dwarkesh Patel** [49:31]
What lessons does this give for 14A in terms of by 2028, it's going to be such a crazy world?

**Chris Auth** [49:36]
Yes.

**Dwarkesh Patel** [49:36]
How do you structure things in such a way that you have flexibility and ramping?

**Chris Auth** [49:40]
Yes. Actually, the way to do it, and we've been doing it, and generally, everybody does it, is you try to maintain as much fungibility as possible going from one node to the next node. So let's say going from 18A to 14A, maybe you would say 80% of the tool set can be reused.

And then, of course, 14A, for example, would require some new capabilities because it's a denser geometry. So it would require some unique tools.

**Dwarkesh Patel** [50:04]
Do you have a sense of what is the ultimate bottleneck of how many wafers you guys could produce a month, even if you decided to invest infinity money into doing CapEx?

**Chris Auth** [50:14]
Given the existing constraints, let's say we had to maximize the output from a given footprint of tools, then I think it's incremental because the process today is already yielding pretty high. And to get if your yield is already pretty high, to get every 1% extra yield is extremely hard because it's already a finely tuned process.

**Dwarkesh Patel** [50:38]
Are there enough tools in the world to say you could 10x the amount of wafers you're producing at the leading edge?

**Chris Auth** [50:43]
Not 10x, but probably like 2x, yes.

**Dwarkesh Patel** [50:45]
That's quite interesting because the AI industry for a decade has been 3x in compute.

**Chris Auth** [50:51]
Yes.

**Dwarkesh Patel** [50:52]
Year over year?

**Chris Auth** [50:52]
Yes.

**Dwarkesh Patel** [50:53]
And you're saying that that just can't continue?

**Chris Auth** [50:55]
Unless the entire supply chain starting from the equipment suppliers, their suppliers, their subsuppliers, unless everybody produces more, you can't increase the output collectively.

**Dwarkesh Patel** [51:08]
Just to give the audience a sense of how big the AI demand is and how well it monetizes the products you guys are producing, you can crunch the numbers. And the number seems to suggest that just a couple billion dollars of CapEx on Intel's account results in enough chips or the logic for enough chips to produce, say, $100 billion of revenue for the AI model companies.

And of course, there's so many other players within that stack. There's also memory and other things. But it's crazy that within a couple billion dollars of CapEx, which can be amortized over many different years, produces $100 billion of revenue every single year, which seems to suggest that at some point, that should percolate down.

And there should be some at some point, the AI labs could just say, we'll just buy every single produce as much as you can. We'll just guarantee future industries and stuff.

**Chris Auth** [51:58]
There's early signs that that could actually be happening already. The demand is just the demand signals are just so high. But I thought you I think you were alluding to how the value is accumulating at the top of the technology stack, which is essentially what is happening is we move from a fully vertically integrated industry like 30, 40 years ago, maybe longer, to a very horizontal industry,right, where you have foundries, you have equipment makers, you have their suppliers.

And today, you think about it, every hyperscaler is designing their own chips. And the scale of the hyperscalers is so large. And some of the model companies, for example, and their demand is so high, yeah, they could easily just consume an entire fab's worth of silicon on their own or multiple fabs' worth of silicon on their own.

And they definitely have the capital to fund that. So in some sense, we are moving from a sort of a horizontal world, again, to a pseudo-vertical world where it's like it's not monolithically vertically integrated, but it's kind of virtually vertically integrated.

**Dwarkesh Patel** [53:14]
Interesting. What is the nature of economies of scale in this business where you look at how many wafers at the leading edge, TSMC versus Intel are shipping, upwards of 3x for TSMC? What kinds of advantages do you get at this point from economies of scale?

Or is it that once you reach a certain point, the economies of scale get weaker?

**Chris Auth** [53:37]
That's a very important question. This entire business

just relies on scale and economies of scale. I mean, if you look at sort of all the advanced manufacturing companies out there, probably semiconductor foundries, the scale economics is probably the purest. And the reason for that is the fixed cost is just so incredibly high that once you build a fab, like 80% of your cost structure is fixed.

And so what that means is every extra percentage of utilization is adding far more in sort of in revenue. So therefore, it's extremely important. And we'll fight for every extra percent of fab utilization, but also every extra percentage of fab output, as in let's say I'm making some wafers today, and the yield is like 60%.

But if I improve the process and the die yield becomes 65% or 70%, it's not a linear advantage. It's like I'm getting way more output for the given footprint,right? So there's always room to improve the economies of scale.

And that's one of the reasons why you're seeing so much consolidation in this business,right? There's only three foundries left at the advanced node for that exact reason. And just along the way, many companies just stop manufacturing. I don't know if you've seen, there's a chart where like 40 years ago, there were like 20 foundries.

And over time, the number of foundries kept diminishing until today, there's only three.

**Dwarkesh Patel** [55:16]
What is basically then the concrete master plan to catch up to TSMC? Even though TSMC is ahead, there's so much overflow demand at their leading edge where N3 is now a majority AI accelerators, maybe a majority NVIDIA alone, that all this demand for CPUs, for other things, which are also, by the way, needed for AI, this humongous influx in demand for CPUs because of AI.

### Catching TSMC

**Dwarkesh Patel** [55:38]
How do you see this opportunityright now where Intel's a few years before, while TSMC is just way over saturated?

**Chris Auth** [55:44]
Catching up to TSMC has maybe has multiple facets. I would say the catch-up that we need to do is in scale. Like you said, they're just a much larger wafer manufacturer today than we are and even bigger than what Samsung is.

Catching up in scale will be a slow process, a gradual process. If you meant catch-up in terms of just the technology, I think that

I think we're already there. We might maybe a few percent off on performance or power or area density. But

this sort of benchmarking of somewhat one foundries ahead or one foundries behind, it makes sense when you're like a whole generation behind or two generations behind or ahead. That's when it makes a meaningful difference in your die output or your die area or functionality like power.

But if you're within like a few percent, it's really

you're splitting hairs at that point in time because it's not very unidimensional at this point. It's not just about density. It's not just about raw performance. Different applications require different vectors. So you can be off by a few percent, but you need to be on time.

Your execution needs to be such that your yields are very high to support very large and very rapid ramps. So that actually is more important than catching up on a few percent in performance or area.

**Dwarkesh Patel** [57:34]
I was looking at some semi-analysis numbers that seem to suggest that in terms of transistor density, 14A, which will come out in like 2028, would be comparable to N2.

**Chris Auth** [57:43]
Yeah. First of all, I would dispute your benchmarking. But like I said, I think it's important to be generally in theright ballpark, be very predictable. And also, it's not unidimensional in terms of we don't build one type of transistor.

Let's say 14A or 18A, you build a few different types of transistors. Let's say there's a low leakage transistor, there's a high performance, high drive current transistor, you're building SRAMs. There's a high density SRAM. There's a high performance SRAM.

There's many other functionalities like some analog circuits, RF circuits. So it's the sum of all of those that makes a technology competitive.

**Dwarkesh Patel** [58:30]
I guess that makes the CapEx you doright now even more important. Soright now, TSMC is on track to do 50 billion in CapEx.

**Chris Auth** [58:36]
Yes.

**Dwarkesh Patel** [58:37]
Around 50 billion in CapEx this year. You're on track to do around 20 billion.

**Chris Auth** [58:40]
Yes.

**Dwarkesh Patel** [58:40]
But if the tools you're buyingright now will determine who can service all this crazy AI demand that's coming up, it makes the CapExright now the difference in CapEx even more important for US versus other countries.

**Chris Auth** [58:52]
Yes, very much. It's a little bit of an unfair comparison between us and TSMC today, just because today they're a foundry for basically everybody. And we're largely a foundry for Intel. We'll become a foundry for others. So in due course, our CapEx will also grow.

**Dwarkesh Patel** [59:11]
Intel started as a DRAM business in the late '60s. And then you guys were producing DRAM, which you sold off. A couple years ago, you sold off your Flash business.

**Chris Auth** [59:22]
Yes.

**Dwarkesh Patel** [59:25]
Yeah, thoughts on that? For context for the audience, these are now multi-trillion dollar industries because they've just exploded as a result of AI demand for them.

**Chris Auth** [59:36]
Yes. I mean, clearly, in hindsight, probably not the smartest time to sell off a Flash memory business. There were good reasons why we did that when we did. Clearly, nobody could see this demand, this enormous demand. But no, today, I think I mean, essentially, the world will eat up as much compute as can possibly be made.

And it'll eat up as much memory as can possibly be made. I would argue that the supply crunch is larger for memory today than it is for compute.

**Dwarkesh Patel** [1:00:13]
So can I summarize what it seems to me the takeaways from your projections are? And you can tell me if that's correct.

**Chris Auth** [1:00:18]
Yes.

**Dwarkesh Patel** [1:00:18]
Marginal production can increase actually very fast on the scale of 12 months. But the amount of increase up till the end of the decade is extremely limited.

**Chris Auth** [1:00:27]
Yes.

**Dwarkesh Patel** [1:00:27]
Production could be higher next year than what people are forecasting. But production in 2030 is not going to be significantly higher than what people are forecasting.

**Chris Auth** [1:00:33]
Unless the entire supply chain ramps up production very quickly. I mean, we're already in the middle of '26. So there's only not that many years until the end of the decade. And given the lead times, let's say you place an enormous order for tools today,right?

And you're looking at, let's say, 18 months to get those tools, you're already into basically '28. And from that point on, if you have to build a new shell, build a new fab, I mean, you're basically looking at the end of the decade.

### Terrafab

**Dwarkesh Patel** [1:01:02]
I think it'll be interesting to discuss the partnership you guys have with Elon on Terrafab. What's going on there?

**Chris Auth** [1:01:11]
Well, I think so Elon's publicly talked about his desire to build a fab.

**Pushkar Arundhate** [1:01:18]
We either build the Terrafab or we don't have the chips. And we need the chips. So we're going to build the Terrafab.

**Chris Auth** [1:01:25]
Sort of the same thinking. I think he's seeing just an enormous increase in demand for silicon, for compute, and for memory. And I think he came to the conclusion that his own businesses are going to require a lot of silicon.

And so he thought maybe he should just do it all on his own. Unlike building a car, for example,

this is such an intricate and complicated process. We thought we could work together to help accelerate his bringing up his fab.

**Dwarkesh Patel** [1:02:00]
But because of the bottleneck at the tool level, it seems like the net amount of silicon in the world won't increase. It's just that maybe if somebody were to start a new fab, they would get access to guaranteed supply in a way that they wouldn't have if they're working with another person's foundry.

**Chris Auth** [1:02:17]
It's actually not just tools. I mean, a fab does require a lot of power, a lot of water, like a lot of consumables. There's many other input variables as well.

**Dwarkesh Patel** [1:02:28]
But those can be scaled in the way that tools cannot.

**Chris Auth** [1:02:30]
Yeah. Some more than others, but yes. But yes, in one sense, yes, we need a lot more equipment. But it is true. I mean, we also need a lot more just raw fab space, raw clean room capacity.

**Dwarkesh Patel** [1:02:47]
So if you think of a foundry like Intel, which has to build these expensive facilities, buy expensive tools, I wonder what you think the economics of that fundamentally could look like, whether it could get more economical, whether it could scale faster.

**Chris Auth** [1:03:01]
Like I described earlier, this is an extremely capital-heavy business. And if you look at the if you just plot the how much does it cost to build a fab? And if you just over the last, I don't know, 20, 30, 40 years, I think it's like doubling every four to five years.

Even inside the fab, if you look at the cost to do lithography, which is the most expensive module, just patterning, that itself is doubling like more than that at more than that rate,right? So like today, a Hi-NA EUV scanner costs like and all its associated equipment is like $400 million,right?

And so what does that mean? If that rate were to continue, if you just draw the line and say, OK, does that mean like four years from now, like cost of patterning is going to be like $800 billion,right?

Doesn't $800 million it doesn't really make sense,right? I think a very interesting thought exercise to do is to say, are there things that could be just very radically different that we could do today that we perhaps couldn't do 20 years ago?

This is a very risk-averse industry for very good reason, for exactly that reason,right? You put in like tens of billions of dollars, and you really don't want to take any risks. So you want to keep doing things the way they've been done for literally decades.

This is not just true of semiconductors, but like everything really. But if you've just kept on doing that for decade upon decade, many things just become like you just become indoctrinated,right? And I mean, there are engineers who probably work at Intel who are new, who just come in and they're taught, this is how the fab, this is the process flow.

And they just take that as gospel,right? That's just how it is done. But is that really the best way to build a chip today? So it's a really valid question.

**Dwarkesh Patel** [1:05:03]
I'm very curious what you're hinting at, because it could be anything from we can figure out ways in which we use fewer lithopasses and economize on this expensive component to like maybe we need to rethink the transistor. What is the level of?

**Chris Auth** [1:05:18]
I think all of the above. Transistor architecture and evolving just the silicon transistor has continued to evolve over 30, 40 years. And that will continue. So you've seen the evolution from the planar transistor to fin fits to now gate all-around transistors.

There'll be more that roadmap is pretty it exists, and it's pretty well-defined. A lot of people working on it. But there's things like, do you really need a clean room today,right? Do you need the infrastructure to be as sophisticated, as complex as it is today?

**Dwarkesh Patel** [1:06:02]
Surely one can run an experiment where you just have people are eating hamburgers and smoking cigars in the research fab and see what happens to yield.

**Chris Auth** [1:06:13]
That would be a great experiment to run, but no incumbent like Intel or TSMC or Samsung. I mean, nobody would want to just willingly do that. So that's what I meant really by this it's a very risk-averse business for good reason.

Every one day lost in productivity is like I don't know how many dollars,right?

**Dwarkesh Patel** [1:06:35]
But you save so much money in not having to build clean rooms in the future.

**Chris Auth** [1:06:38]
But it's really the risk of the fear of the unknown,right? So nobody is going to willingly take that risk. But that's why I think sometimes it's good to sort of just start with a clean slate and rethink everything.

And it's like, OK, these things same thing applies to chip design, by the way,right? Many of the ways we do CPU design were probably locked in like 30 years ago. Does that mean it's smart to still do it the same way?

Probably not,right? But this is a very complex problem. Chip design is like easy to it's fairly low

I guess the capacity to take risk is maybe higher. This one, less so. But given where the economics is today, I think it's a very valid question to ask. Maybe there's a smarter way to do this.

**Dwarkesh Patel** [1:07:39]
So to close out, maybe we'll start off at the same question we began the interview with, which is, how does Intel respond to this crazy AI demand that's incoming and has already arrived? And it sounds like what Intel ought to do if the ultimate bottleneck is you guys already have these foundries.

You guys already have the ability to expand these foundries. But what you will eventually lack is the tools from upstream in the supply chain to just raise as much capital as possibleright now, the same way that Nvidia has locked down memory and other components for reportedly hundreds of billions of dollars worth of commitments that it's made.

**Chris Auth** [1:08:19]
Yes.

**Dwarkesh Patel** [1:08:20]
Intel should maybe do the same thing, make all these commitments so that as over the coming years, the US is in good position to have the bulk of semiconductor manufacturing at the most advanced levels happening here.

**Chris Auth** [1:08:33]
You're suggesting we should be buying a lot more tools,right?

**Dwarkesh Patel** [1:08:36]
Yeah, because it sounds like it's just like, well, in a couple of years, otherwise, you'd just be in a position where you're like, oh, man, we could be making trillions of dollarsright now. But all the tools are in Taiwan.

**Chris Auth** [1:08:45]
Yes. I mean, no, that's a very, very valid question. Had we known what we know today, we would have bought invested more like a year ago. Knowing what we know now, I think we'll be investing more.

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